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24-bit capacitance-to-digital converter with temperature sensor ad7745/ad7746 rev. 0 in fo rmation furn ished by an al o g d e v i ces is believed to be accurate and reliab le. how e ver, n o respo n sibili ty is assume d b y a n alo g d e vices f o r its use, no r f o r a n y i n fri n geme nt s of p a t e nt s or ot her ri g h t s o f th ird parties th at may result fro m its use . specifications subjec t to chan ge with out n o tice. no licen s e is g r an te d by implicatio n or ot her w i s e und e r a n y p a t e nt or p a t e nt ri ghts of analo g dev i ces. tradema r ks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features capacitance-to-digital conver ter new standard i n single chip solutions interfaces to si ngle or differential floating s e nsors resolution down to 4 af (tha t is, up to 2 1 e n ob) accu racy : 4 ff linearity: 0.0 1 % common-mod e (not changing) capacitance u p to 17 pf full-scal e (cha nging) capa cit a nce range: 4 pf tolerant of parasitic capacitance to ground up to 60 pf update rat e : 1 0 hz to 90 hz simultaneous 50 hz and 60 h z rejection at 1 6 hz temperature s e nsor on-chip resolution: 0.1c, accuracy: 2c voltage input c h annel internal clock oscillator 2-wire seri al in terface (i 2 c ? -compatible) power 2.7 v to 5.25 v single-supply o p eration 0.7 ma c u rrent consumption operating temperature: C4 0 c to +12 5 c 16-lea d tssop package applic ati o ns automotive, in dustria l , and m e dical s y stems for pressure m eas urement position sensing level sensing flowmeters h u m i d i ty s e n sin g impurity detection general description the ad7745/ad7746 a r e a hig h r e s o l u tio n , - c a p a ci tance-to- dig i t a l con v er t e r (cd c ). the c a p a ci t a n c e t o b e m e as ur e d is co nne c t e d dir e c t ly to t h e d e vi ce in p u t s . t h e a r chi t e c t u r e fe a- tu re s i n he re n t h i g h re s o lut i o n ( 2 4 - bit no m i ss i n g c o d e s , up to 21-b i t ef f e c t i v e r e s o l u tio n ), hig h lin e a r i t y (0.0 1 %), a nd hig h acc u rac y (4 ff fac t o r y cali b r a t e d ). the ad7745 /ad7746 c a p a c i t a nc e i n put r a nge i s 4 p f ( c h a ng i n g ) , w h i l e i t c a n a c c e pt u p t o 17 pf co mm on-mo d e c a p a ci tan c e ( n o t cha n g i n g ), whic h ca n be bala n c ed b y a p r ogra m m a b l e o n -c h i p , d i gi tal-t o - ca p a c i tan c e con v er t e r (cap d a c). the ad7745 has o n e ca p a c i tance in p u t c h a n nel , while t h e ad7746 has two c h a nne ls. e a c h c h a n ne l can b e co nf igur ed as sin g le-en d e d o r dif f er en tia l . th e ad7745/ad77 46 a r e desig n e d f o r f l oa ti n g ca pa ci ti v e se n s o r s. f o r ca pa ci ti v e s e n s o r s wi th o n e p l a t e co nn ec ted t o g r o u n d , t h e ad7747 is r e commende d . the p a r t s ha v e a n o n -chi p t e m p era t ur e s e n s o r wi t h a r e s o l u t i on of 0 . 1 c an d a c c u r a c y of 2 c . t h e on - c h i p vo lt age re f e re nc e a nd t h e o n -chi p clo c k g e nera t o r e l imina t e t h e ne e d fo r a n y ext e r n al co m p on en ts in c a p a ci t i v e s e n s o r a p p l ica t ion s . th e p a r t s ha v e a st anda r d v o l t a g e i n p u t, w h ich t o g e t h er wi t h t h e dif f er en t i al r e fe r e n c e i n p u t al lo ws e a sy in t e r f ac e t o a n ext e r n al t e m p era t ur e s e ns o r , s u ch as a n r t d , t h er mis t or , o r dio d e . the ad7745/ad7746 ha v e a 2-wir e , i 2 c- co m p a t i b le s e r i al in t e r f ace . b o t h p a r t s ca n o p er a t e w i t h a sin g le p o w e r s u p p l y f r o m 2.7 v t o 5.25 v . they a r e sp ecif ied o v er the a u t o m o ti v e t e m p era t ur e ra ng e o f C40c t o +125c an d a r e h o us e d in a 16-lead t sso p p a c k a g e . func tio n a l block di agrams digital filter 24-bit - ? modulator clock generator mux temp sensor cap dac cap dac voltage reference control logic calibration ad7745 vdd refin(+) refin(? ) gnd sda scl rdy vin(+) vin(? ) cin1(+) cin1( ? ) exca excb 05468-001 i 2 c serial interface excitation fi g u r e 1 . digital filter 24-bit - ? modulator mux temp sensor cap dac cap dac voltage reference control logic calibration ad7746 vdd refin(+) refin(? ) gnd sda scl rdy vin(+) vin(? ) cin1(+) cin1( ? ) cin2(+) cin2( ? ) exc1 exc2 05468-002 clock generator i 2 c serial interface excitation fi g u r e 2 .
ad7745/ad7746 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 output noise and resolution specifications .............................. 11 serial interface ................................................................................ 12 read operation ........................................................................... 12 write operation .......................................................................... 12 ad7745/ad7746 reset ............................................................. 13 general call ................................................................................. 13 register descriptions ..................................................................... 14 status register ............................................................................. 15 cap data register ....................................................................... 15 vt data register ........................................................................ 15 cap set-up register ................................................................... 16 vt set-up register .................................................................... 16 exc set-up register .................................................................. 17 configuration register .............................................................. 18 cap dac a register ................................................................... 19 cap dac b register ................................................................... 19 cap offset calibration register ................................................ 19 cap gain calibration register .................................................. 19 volt gain calibration register ................................................. 19 circuit description ......................................................................... 20 overview ..................................................................................... 20 capacitance-to-digital converter ........................................... 20 excitation source ........................................................................ 20 capdac ..................................................................................... 21 single-ended capacitive input ................................................. 21 differential capacitive input .................................................... 21 parasitic capacitance to ground .............................................. 22 parasitic resistance to ground ................................................. 22 parasitic parallel resistance ...................................................... 22 parasitic serial resistance ......................................................... 23 capacitive gain calibration ..................................................... 23 capacitive system offset calibration ...................................... 23 internal temperature sensor .................................................... 23 external temperature sensor ................................................... 24 volt age input ............................................................................... 24 v dd monitor ................................................................................ 24 typical application diagram .................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 4/05revision 0: initial version
ad7745/ad7746 rev. 0| page 3 of 28 specifications v dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; gnd = 0 v; exc = 32 khz; exc = v dd /2; C40c to +125c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments capacitive input conversion input range 4.096 pf 1 factory calibrated integral nonlinearity (inl) 2 0.01 % of fsr no missing codes 2 24 bit conversion time 62 ms resolution, p-p 16.5 bit conversion time = 62 ms, see table 5 resolution effective 19 bit con version time = 62 ms, see table 5 output noise, rms 2 af/ hz see table 5 absolute error 3 4 f f 1 25c, v dd = 5 v, after offset calibration offset error 2 , 4 32 af 1 after system offset calibration, excluding effect of noise 4 system offset calibration range 2 1 p f offset drift vs. temperature C1 af/c gain error 5 0.02 0.08 % of fs 25c, v dd = 5 v gain drift vs. temperature 2 C28 C26 C24 ppm of fs/c allowed capacitance to gnd 2 60 pf see figure 9 and figure 10 power supply rejection 0.3 1 ff/v normal mode rejection 65 db 50 hz 1%, conversion time = 62 ms 55 db 60 hz 1%, conversion time = 62 ms channel-to-channel isolation 70 db ad7746 only capdac full range 17 21 pf resolution 6 164 ff 7-bit capdac drift vs. temperature 2 24 26 28 ppm of fs/c excitation frequency 32 khz voltage across capacitance v dd /8 v configurable via digital interface v dd /4 v v dd 3/8 v v dd /2 v average dc voltage across capacitance <40 mv allowed capacitance to gnd 2 100 pf see figure 11 temperature sensor 7 v ref internal resolution 0.1 c error 2 0.5 2 c internal temperature sensor 2 c external sensing diode 8 voltage input 7 v ref internal or v ref = 2.5 v differential vin voltage range v ref v absolute vin voltage 2 gnd ? 0.03 v dd + 0.03 v integral nonlinearity (inl) 3 15 ppm of fs no missing codes 2 24 bit conversion time = 122.1 ms resolution, p-p 16 bits conversion time = 62 ms see table 6 and table 7 output noise 3 v rms conversion time = 62 ms see table 6 and table 7 offset error 3 v offset drift vs. temperature 15 nv/c full-scale error 2 , 9 0.025 0.1 % of fs
ad7745/ad7746 rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments full-scale drift vs. temperature 5 ppm of fs/c internal reference 0.5 ppm of fs/c external reference average vin input current 300 na/v analog vin input current drift 50 pa/v/c power supply rejection 80 db internal reference, v in = v ref /2 power supply rejection 90 db external reference, v in = v ref /2 normal mode rejection 75 db 50 hz 1%, conversion time = 122.1 ms 50 db 60 hz 1%, conversion time = 122.1 ms common-mode rejection 95 db v in = 1 v internal voltage reference voltage 1.169 1.17 1.171 v t a = 25c drift vs. temperature 5 ppm/c external voltage reference input differential refin voltage 2 0.1 2.5 v dd v absolute refin voltage 2 gnd ? 0.03 v dd + 0.03 v average refin input current 400 na/v average refin input current drift 50 pa/v/c common-mode rejection 80 db serial interface logic inputs (scl, sda) v ih input high voltage 2.1 v v il input low voltage 0.8 v hysteresis 150 mv input leakage current (scl) 0.1 1 a open-drain output (sda) v ol output low voltage 0.4 v i sink = ? 6.0 ma i oh output high leakage current 0.1 1 a v out = v dd logic output ( rdy ) v ol output low voltage 0.4 v i sink = 1.6 ma, v dd = 5 v v oh output high voltage 4.0 v i source = 200 a, v dd = 5 v v ol output low voltage 0.4 v i sink = 100 a, v dd = 3 v v oh output high voltage v dd C 0.6 v i source = 100 a, v dd = 3 v power requirements v dd -to-gnd voltage 4.75 5.25 v v dd = 5 v, nominal 2.7 3.6 v v dd = 3.3 v, nominal i dd current 850 a digital inputs equal to v dd or gnd 750 a v dd = 5 v 700 a v dd = 3.3 v i dd current power-down mode 0.5 2 a digital inputs equal to v dd or gnd 1 capacitance units: 1 pf = 10 -12 f; 1 ff = 10 -15 f; 1 af = 10 -18 f. 2 specification is not production tested, but is supported by characterization data at initial product release. 3 factory calibrated. the absolute error includes factory gain calibration error, integral nonlin earity error, and offset error after system offset calibration, all at 25c. at different temperatures, compensation for g ain drift over temperature is required. 4 the capacitive input offset can be eliminated using a system offset calibration. the accuracy of the system offset calibration is limited by the offset calibration register lsb size (32 af) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. to m inimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. the system capacitance offset ca libration range is 1 pf, the larger offset can be removed using capdacs. 5 the gain error is factory calibrated at 25c. at different temperatures, compensation for gain drift over temperature is requi red. 6 the capdac resolution is seven bits in the actual capdac full range. using the on-chip offset calibration or adjusting the cap acitive offset calibration register can further reduce the cin offset or the unchanging cin component. 7 the vtchop bit in the vt setup register must be set to 1 for the specified temperature sensor and voltage input performance. 8 using an external temper ature sensing diode 2n3906, with nonideality factor n f = 1.008, connected as in figure 41, with total serial resistance <100 ?. 9 full-scale error applies to both positive and negative full scale.
ad7745/ad7746 rev. 0| page 5 of 28 timing specifications v dd = 2.7 v t o 3.6 v , o r 4.75 v t o 5.25 v ; gnd = 0 v ; i n p u t l o g i c 0 = 0 v ; i n p u t l o g i c 1 = v dd ; C 4 0 c to + 1 2 5 c , u n l e ss ot h e r w i s e note d. table 2. p a r a m e t e r m i n t y p m a x u n i t t e s t condition s / c o m m e n t s serial i n te rfa c e 1 , 2 see f i g u r e 3 scl frequency 0 400 khz scl high pulse width, t high 0 . 6 s scl low pulse width, t low 1 . 3 s scl, sda rise ti me, t r 0 . 3 s scl, sda fall time, t f 0 . 3 s hold time (start condition), t hd;sta 0.6 s after this period, the first clock is generated set-up time (start condition), t su ;st a 0.6 s relevant for repeated start condition data set-up time, t su ;dat 0 . 2 5 s v dd 3.0 v data set-up time, t su ;dat 0 . 3 5 s v dd < 3.0 v set-up time (stop condition), t su ;st o 0 . 6 s data hold time, t hd;dat (mas t er) 0 s bus-free time (between stop a n d start conditi o n, t buf ) 1 . 3 s 1 sampl e tes t ed d uri ng initial rel e ase to ens ure compl iance. 2 al l input s i gnal s are s p ecif ied with input ris e /f al l times = 3 ns , mea s ured b e tween the 10% and 9 0 % points . timing ref e rence p oi n t s a t 50% for i n put s a n d out p ut s. out p ut loa d = 10 p f. p s t low t r t f t hd:sta t hd:dat t su:dat t su:sta t hd:sta t su:sto t high scl ps sd a t buf 05468-003 f i g u re 3. s e r i a l in te r f ac e ti m i ng d i ag r a m
ad7745/ad7746 rev. 0 | page 6 of 2 8 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g positive supply voltage v dd to g n d ? 0.3 v to +6.5 v voltage on any input or output pin to gnd C0.3 v to v dd + 0.3 v esd rating ( e sd association human body model, s5.1) 2000 v operating tem p erature range C40c to +125c storage temperature range C65c to +150c junction tempe r ature 150c tssop package ja , (thermal impedance-to-air) 128c/w tssop package jc , (thermal impedance-to-cas e) 14c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . es d c a u t io n esd (electrostatic discharge) se nsitive device. electrosta tic char ges as high as 4 000 v readily accumulate on the human body and test eq uipment and c a n d i scharge wit h out d e tection. although th is product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
ad7745/ad7746 rev. 0| page 7 of 28 pin conf igurations and f u ncti on descriptions 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ad7745 top view (not to scale) scl exca excb refin(+) refin(? ) cin1(? ) cin1(+) rdy sda vdd gnd vin( ? ) vin(+) nc nc nc nc = no connect 05468-004 f i g u re 4. a d 77 45 p i n conf ig ur at io n (1 6-l e ad t ssop ) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ad7746 top view (not to scale) scl exca excb refin(+) refin(?) cin1(?) cin1(+) rdy sda vdd gnd vin(? ) vin(+) cin2(? ) cin2(+) nc nc = no connect 05468-005 f i g u re 5. a d 77 46 p i n conf ig ur at io n (1 6-l e ad t ssop ) ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1 s c l serial interface clock input. connects to the master cloc k line . requires pull-u p resistor if not alread y provided in the system. 2 rdy logic output. a falling edge on this output indicates that a conversion o n enab l e d channel( s) ha s been finished and the new data is avai labl e. alternativ ely, the status register can be re ad via the 2-wire serial interface and the relevant bit(s) decode d to que r y the finished conversi on. if not used, this pin should be left as an o p en circu i t. 3, 4 exca, excb cdc ex citation outputs. the m e asured capacit a nce is c o nnect ed between one of the exc pins and one of the cin pins. if not used, these pins s h ould be left as an open c i rcuit. 5, 6 refin(+), refin(C ) differential voltage reference input for the voltage ch annel (adc). alternatively, the on-chip internal reference can b e used for the v o ltage chan nel. these reference input pins are n o t used for conversion o n capacitive c h an nel(s) (cdc). if n o t used, these pins ca n be left as an open c i rcuit or conne cted to gnd. 7 c i n 1 ( C ) cdc negative capacitive input i n differential m o d e . t h is pin is i n ternally d i sco n nected in single -end ed cdc configuration. if not used, this pin can be le ft as an open circuit or connected to gnd. 8 c i n 1 ( + ) cdc capacitive input (in singl e -ended mode ) or pos i tive capacit i ve input (in di ff erential mode). the measured capac i tance is co nnec t ed between on e of the ex c pins and one of the cin pins. if not used, this pin can be left as a n open circuit or connected to gnd. 9, 10 (ad7745) nc not connected. this pin sh ould be left as an open circuit. 9 (ad7746) cin2(+ ) cdc second capacitive input (in single-ended mode) or po sitive capacitive input (in di f f erential mode). if not used, this pin ca n be left open ci rcuit or connect ed to gnd. 10 (ad7746) cin2(C) cdc negative c a pacitive input in differe ntial mode. this pin is i n ternally disco n nected in a singl e -ended cdc configuration. if not used, this pin can be le ft as an open circuit or connected to gnd. 11, 12 vin(+), vin( C) differential voltage input for th e voltage chan nel ( a dc) . these pins are a lso used to connect an external temperature se nsing diode. if not used, these pins ca n be left as an open c i rcuit or conne cted to gnd. 1 3 g n d g r o u n d p i n . 1 4 v d d power supply voltage. t h is pin should be d e co upled to gnd, using a lo w impe d ance capa citor , for examp l e in combin ation with a 10 f tantalum and a 0.1 f multilayer ceramic. 15 nc not connected. this pin sh ould be left as an open circuit. 1 6 s d a serial interface bidirectional data. connects to the master d a ta l i ne. requires a p u ll-up resistor if not provid ed elsewhere in th e system.
ad7745/ad7746 rev. 0 | page 8 of 2 8 typical perf orm ance cha r acte ristics 100 0 ?5 5 05468-014 input capacitance (pf) inl (ppm) 80 60 40 20 ?4 ? 3 ?2 ? 1 0 1 2 3 4 f i gure 6 . c a p a ci tanc e input int e g r al no nl i n eari t y , v dd = 5 v , t h e s a me conf ig u r at ion as i n f i g u r e 3 1 2000 ?3000 ? 5 0 150 05468-015 temperature (c) gain e rror (ppm) 1000 0 ?1000 ?2000 ? 2 5 0 25 50 75 100 125 gain tc ?26ppm/c f i gure 7 . c a p a ci tanc e input o ffset drif t vs . t e m p er a t ure , v dd = 5 v , cin and ex c p i ns o p en c i rcuit 100 ?100 ? 5 0 150 05468-016 temperature (c) offs e t e rror (a f) 75 50 25 0 ?2 5 ?5 0 ?7 5 ? 2 5 0 25 50 75 100 125 f i gure 8 . c a p a ci tanc e input g a i n dri f t vs . t e m p er a t ure , v dd = 5 v , cin(+) to e x c = 4 pf , the s a me configu r at io n as in f i gu r e 3 0 18 ?2 0 500 05468-017 capacitance cin pin to gnd (pf) cap acitance e rror (ff) 16 14 12 10 8 6 4 2 0 50 100 150 200 250 300 350 400 450 2.7v 3v 5v 3.3v f i gure 9. cap a c i ta nc e input e r ror v s . capa cita nc e b e t w e e n cin and gnd . cin(+) to ex c = 4 p f , cin(?) to ex c = 0 pf , v dd = 2 . 7 v, 3 v, 3 . 3 v, a n d 5 v, t h e s a m e conf ig u r at io n as in f i g u r e 3 3 18 ?2 0 500 05468-018 capacitance cin pin to gnd (pf) cap acitance e rror (ff) 16 14 12 10 8 6 4 2 0 50 100 150 200 250 300 350 400 450 2.7v 3v 3.3v 5v f i gure 10. cap a c i ta nc e input e r ror v s . capa cita nc e b e t w e e n cin and gnd , cin(+) to ex c = 21 pf , cin(?) to ex c = 23 pf , v dd = 2.7 v , 3 v , 3. 3 v , and 5 v , t h e s a m e conf ig ur at io n as in f i g u r e 3 4 5 ?1 0 500 05468-019 capacitance exc pin to gnd (pf) cap acitance e rror (ff) 4 3 2 1 0 50 100 150 200 250 300 350 400 450 2.7v 3v 5v 3.3v f i gure 11. cap a c i ta nc e input e r ror v s . capa cita nc e b e t w e e n e x c and g n d , cin(+) to ex c = 21 pf , cin(?) to ex c = 23 pf , v dd = 2.7 v , 3 v , 3. 3 v , and 5 v , t h e s a m e conf ig ur at io n as in f i g u r e 3 4
ad7745/ad7746 rev. 0| page 9 of 28 8 ?1 2 ? 250 250 05468-028 cin leakage to gnd (na) cap acitance e rror (ff) 2.7v 3v 6 4 2 0 ?2 ?4 ?6 ?8 ?1 0 ?200 ? 150 ?100 ? 5 0 0 50 100 150 200 f i gure 12. cap a c i ta nc e input e r ror v s . l e akage cu rrent to gnd , cin(+) to ex c = 4 p f , cin(?) to ex c = 0 pf , v dd = 2. 7 v and 3 v 8 ?1 2 ? 250 250 05468-030 cin leakage to gnd (na) cap acitance e rror (ff) 6 4 2 0 ?2 ?4 ?6 ?8 ?1 0 ?200 ? 150 ?100 ? 5 0 0 50 100 150 200 3.3v 5v f i gure 13. cap a c i ta nc e input e r ror v s . l e akage cu rrent to gnd , cin(+) to e x c =4 pf , cin(?) to e x c = 0 pf , v dd=3 . 3 v and 5 v 10 0.0001 1 100000 05468-029 parallel resistance (m ? ) cap acitance e rror (pf) 1 0.1 0.01 0.001 10 100 1000 10000 f i gure 14. cap a c i ta nc e input e r ror v s . r e s i s t anc e in p a r a l l e l with me asured ca pac i tance 0 ?1 0 07 05468-031 serial resistance (k ? ) cap acitance e rror (ff) ?2 ?4 ?6 ?8 12345 6 f i gure 15. cap a c i ta nc e input e r ror v s . s e r i a l r e s i s t ance , cin(+) to ex c = 21 pf , cin(?) to ex c = 23 pf , v dd = 5 v , t h e s a m e conf ig ur at io n as in f i g u r e 3 4 . 0.2 ?1.0 2.5 5.5 05468-032 v dd (v) cap acitance e rror (ff) 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 3.0 3.5 4.0 4.5 5.0 f i gure 16. c a p a c i tanc e input p o wer su p p ly rej e c t ion ( p sr ), cin(+) to ex c = 4 p f , the s a me config ur ation as in f i gure 30 0.20 ? 0.20 0 128 05468-033 capdac code cap dac code dnl (pf) 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 16 32 48 64 80 96 112 f i g u re 17. ca pda c d i f f e r e nt ia l non l i n ear i t y ( d nl)
ad7745/ad7746 rev. 0 | page 10 of 28 2.0 ?2.0 ? 5 0 150 05468-034 temperature (c) e rror ( c) 1.5 1.0 0.5 0 ? 0.5 ? 1.0 ? 1.5 ? 2 5 0 25 50 75 100 125 f i gure 18. inte rn al t e m p er ature s e nso r e rror v s . t e m p er at ur e 1.0 ?3.0 ? 5 0 150 05468-035 temperature (c) e rror ( c) 0.5 0 ? 0.5 ? 1.0 ? 1.5 ? 2.0 ? 2.5 ? 2 5 0 25 50 75 100 125 f i gure 19. e x ter n a l t e m p er ature s e nso r e rror v s . t e m p er at ur e 0 ?120 0 1000 05468-036 input signal frequency (hz) gain ( d b) ?2 0 ?4 0 ?6 0 ?8 0 ?100 100 200 300 400 500 600 700 800 900 fi g u r e 2 0 . c a p a c i t a n c e c h a n n e l fr e q u e n c y r e s p o n s e , convers i on tim e = 11 ms 0 ?120 0 400 05468-037 input signal frequency (hz) gain ( d b) ?2 0 ?4 0 ?6 0 ?8 0 ?100 50 100 150 200 250 300 350 fi g u r e 2 1 . c a p a c i t a n c e c h a n n e l fr e q u e n c y r e s p o n s e , convers i on tim e = 62 ms 0 ?120 0 400 05468-038 input signal frequency (hz) gain ( d b) ?2 0 ?4 0 ?6 0 ?8 0 ?100 50 100 150 200 250 300 350 fi g u r e 2 2 . c a p a c i t a n c e c h a n n e l fr e q u e n c y r e s p o n s e , convers i on tim e = 10 9. 6 ms 0 ?120 0 400 05468-039 input signal frequency (hz) gain ( d b) ?2 0 ?4 0 ?6 0 ?8 0 ?100 50 100 150 200 250 300 350 f i g u re 23. v o lt ag e chann e l f r equenc y r e s p ons e , convers i on tim e = 12 2. 1 ms
ad7745/ad7746 rev. 0| page 11 of 28 output noise and resolu tion specifications the ad7745/ad7746 resolution is limited by noise. the noise performance varies with the selected conversion time. table 5 shows typical noise performance and resolution for the capacitive channel. these numbers were generated from 1000 data samples acquired in continuous conversion mode, at an excitation of 32 khz, v dd /2, and with all cin and exc pins connected only to the evaluation board (no external capacitors.) table 6 and table 7 show typical noise performance and resolution for the voltage channel. these numbers were generated from 1000 data samples acquired in continuous conversion mode with vin pins shorted to ground. rms noise represents the standard deviation and p-p noise represents the difference between minimum and maximum results in the data. effective resolution is calculated from rms noise, and p-p resolution is calculated from p-p noise. table 5. typical capacitive input noise and resolution vs. conversion time conversion time (ms) output data rate (hz) C3db frequency (hz) rms noise (af/hz) rms noise (af) p-p noise (af) effective resolution (bits) p-p resolution (bits) 11.0 90.9 87.2 4.3 40.0 212.4 17.6 15.2 11.9 83.8 79.0 3.1 27.3 137.7 18.2 15.9 20.0 50.0 43.6 1.8 12.2 82.5 19.4 16.6 38.0 26.3 21.8 1.6 7.3 50.3 20.1 17.3 62.0 16.1 13.8 1.5 5.4 33.7 20.5 17.9 77.0 13.0 10.5 1.5 4.9 28.3 20.7 18.1 92.0 10.9 8.9 1.5 4.4 27.8 20.8 18.2 109.6 9.1 8.0 1.5 4.2 27.3 20.9 18.2 table 6. typical voltage input nois e and resolution vs. conversion time, internal voltage reference conversion time (ms) output data rate (hz) C3db frequency (hz) rms noise (v) p-p noise (v) effective resolution (bits) p-p resolution (bits) 20.1 49.8 26.4 11.4 62 17.6 15.2 32.1 31.2 15.9 7.1 42 18.3 15.7 62.1 16.1 8.0 4.0 28 19.1 16.3 122.1 8.2 4.0 3.0 20 19.5 16.8 table 7. typical voltage input noise and resolution vs. conversion time , external 2.5 v voltage reference conversion time (ms) output data rate (hz) C3db frequency (hz) rms noise (v) p-p noise (v) effective resolution (bits) p-p resolution (bits) 20.1 49.8 26.4 14.9 95 18.3 15.6 32.1 31.2 15.9 6.3 42 19.6 16.8 62.1 16.1 8.0 3.3 22 20.5 17.7 122.1 8.2 4.0 2.1 15 21.1 18.3
ad7745/ad7746 rev. 0 | page 12 of 28 serial interface the ad7745/ad7746 supports an i 2 c-compatible 2-wire serial interface. the two wires on the i 2 c bus are called scl (clock) and sda (data). these two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. the sda wire carries the data, while the scl wire synchronizes the sender and receiver during the data transfer. i 2 c devices are classified as either master or slave devices. a device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. to control the ad7745/ad7746 device on the bus, the following protocol must be followed. first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that the start byte follows. this 8-bit start byte is made up of a 7-bit address plus an r/w bit indicator. all peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address + r/w bit). the bits arrive msb first. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. an exception to this is the general call address, which is described later in this document. the idle condition is where the device monitors the sda and scl lines waiting for the start condition and the correct address byte. the r/w bit determines the direction of the data transfer. a logic 0 lsb in the start byte means that the master writes information to the addressed peripheral. in this case the ad7745/ad7746 becomes a slave receiver. a logic 1 lsb in the start byte means that the master reads information from the addressed peri- pheral. in this case, the ad7745/ad7746 becomes a slave transmitter. in all instances, the ad7745/ad7746 acts as a standard slave device on the i 2 c bus. the start byte address for the ad7745/ad7746 is 0x90 for a write and 0x91 for a read. read operation when a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the sda line by the ad7745/ad7746. this is then clocked out by the master device and the ad7745/ad7746 awaits an acknowledge from the master. if an acknowledge is received from the master, the address auto- incrementer automatically increments the address pointer register and outputs the next addressed register content on to the sda line for transmission to the master. if no acknowledge is received, the ad7745/ad7746 return to the idle state and the address pointer is not incremented. the address pointers auto-incrementer allow block data to be written or read from the starting address and subsequent incremental addresses. in continuous conversion mode, the address pointers auto- incrementer should be used for reading a conversion result. that means, the three data bytes should be read using one multibyte read transaction rather than three separate single byte transactions. the single byte data read transaction may result in the data bytes from two different results being mixed. the same applies for six data bytes if both the capacitive and the voltage/temperature channel are enabled. the user can also access any unique register (address) on a one- to-one basis without having to update all the registers. the address pointer register contents cannot be read. if an incorrect address pointer location is accessed or, if the user allows the auto-incrementer to exceed the required register address, the following applies: ? in read mode, the ad7745/ad7746 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. the address pointers auto-incrementers contents are reset to point to the status register at address 0x00 when a stop condition is received at the end of a read operation. this allows the status register to be read (polled) continually without having to constantly write to the address pointer. ? in write mode, the data for the invalid address is not loaded into the ad7745/ad7746 registers but an acknowledge is issued by the ad7745/ad7746. write operation when a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the ad7745/ ad7746. the address pointer byte is automatically loaded into the address pointer register and acknowledged by the ad7745/ ad7746. after the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. a stop condition is defined by a low-to-high transition on sda while scl remains high. if a stop condition is ever encountered by the ad7745/ad7746, it returns to its idle condition and the address pointer is reset to address 0x00. if a data byte is transmitted after the register address pointer byte, the ad7745/ad7746 load this byte into the register that is currently addressed by the address pointer register, send an acknowledge, and the address pointer auto-incrementer auto- matically increments the address pointer register to the next internal register address. thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses.
ad7745/ad7746 rev. 0| page 13 of 2 8 i f a r e p e a t e d st ar t co n d i t io n is e n co u n t e r e d a f t e r t h e ad dr ess p o i n te r b y te, a l l p e r i phe r a l s c o n n e c t e d to t h e b u s re sp ond exac t l y as o u t l ine d ab o v e fo r a st a r t co n d i t ion, t h a t is, a r e p e a t e d st a r t co ndi t i o n i s t r e a te d t h e s a m e as a st a r t con d i t ion. w h en a maste r d e v i c e is su e s a stop c o ndi t i on, i t rel i nqu i she s c o n t rol of th e b u s, allo w i n g a n o t h e r m a s t er d evi ce t o ta k e co n t r o l o f th e b u s. h e nce , a mas t er wan t in g t o r e ta in con t r o l o f th e b u s iss u es successi ve st a r t co ndi t i on s k n o w n as r e p e a t e d st a r t co ndi t i o n s . ad7745/ad7746 reset t o r e s e t t h e ad7745/ad7746 wi t h o u t ha vin g t o r e s e t th e en tir e i 2 c b u s, a n expli c i t r e s e t co m m and is p r o v ide d . this us es a p a r t ic u l a r addr ess p o i n t e r w o r d as a co m m an d w o r d t o r e s e t t h e p a r t a n d u p lo ad al l defa u l t s e t t in gs. the ad774 5/ad7746 do not re s p o n d to t h e i 2 c b u s co m m a nds (do n o t ack n o w le dge) d u r i n g the def a u l t val u es u p lo ad f o r a p p r o x ima t e l y 150 s (max 200 s). the r e s e t co m m a nd ad dr ess wo r d is 0x bf . general call w h en a mast er is s u es a s l a v e addr es s co n s is t i n g o f s e v e n 0s w i t h t h e ei g h t h b i t ( r /w b i t) s e t t o 0, t h is is k n o w n as t h e ge n e ra l c a l l addr ess. t h e ge n e r a l c a l l addr e s s is fo r addr essin g e ver y de vic e co nne c t e d to t h e i 2 c b u s. th e ad7745/ad7746 ac kn o w le dg e t h is addr ess and r e ad in t h e fol l o w in g d a t a b y te. i f th e s e cond b y t e is 0x06, th e ad7745/ad7746 a r e r e s e t, co m p lete l y u p lo adin g al l defa u l t val u es. the ad7745/ad7746 do n o t r e sp o nd to t h e i 2 c b u s c o mman d s (do no t ac k n o w le dg e ) d u r i n g the def a u l t val u es u p lo ad f o r a p p r o x ima t e l y 150 s (max 200 s). the ad7745/ad7746 do n o t ac kn o w ledge an y o t h e r g e n e ral ca l l co mman d s. 1? 7 8 9 1 ?7 8 9 1?7 8 9 p s start addr r/w ack subaddress ack data ack stop sdata sclock 05468-006 f i gur e 2 4 . bus da t a t r a n sfer data a(s) s s l a v e ad dr a( s ) s u b add r a(s) lsb = 0 lsb = 1 data p s s l a v e ad dr a( s ) s u b a ddr a ( s ) s s l a v e addr a( s ) d a t a a(m) data p write sequence read sequence a(s) = no-acknowledge by slave a(m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit a(s) a(m) 05468-007 f i gure 25. w r ite an d read s e qu enc e s
ad7745/ad7746 rev. 0 | page 14 of 28 register descriptions the master can write to or read from all of the ad7745/ ad7746 registers except the address pointer register, which is a write-only register. the address pointer register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the address pointer register. after the part has been accessed over the bus and a read/write operation is selected, the address pointer register is set up. the address pointer register determines from or to which register the operation takes place. a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. table 8. register summary address pointer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register (dec) (hex) dir default value - - - - excerr rdy rdyvt rdycap status 0 0x00 r 0 0 0 0 0 1 1 1 cap data h 1 0x01 r capacitive channel datahigh byte, 0x00 cap data m 2 0x02 r capacitive channe l datamiddle byte, 0x00 cap data l 3 0x03 r capacitive channe l datalow byte, 0x00 vt data h 4 0x04 r voltage/temperature channel datahigh byte, 0x00 vt data m 5 0x05 r voltage/temperature ch annel datamiddle byte, 0x00 vt data l 6 0x06 r voltage/temperature channel datalow byte, 0x00 capen cin2 1 capdiff - - - - capchop cap setup 7 0x07 r/w 0 0 0 0 0 0 0 0 vten vtmd1 vtmd0 extref - - vtshort vtchop vt setup 8 0x08 r/w 0 0 0 0 0 0 0 0 clkctrl excon excb excb exca exca exclvl1 exclvl0 exc setup 9 0x09 r/w 0 0 0 0 0 0 1 1 vtfs1 vtfs0 capfs2 capfs1 capfs0 md2 md1 md0 configuration 10 0x0a r/w 1 0 1 0 0 0 0 0 dacaena daca7-bit value cap dac a 11 0x0b r/w 0 0x00 dacbenb dacb7-bit value cap dac b 12 0x0c r/w 0 0x00 cap offset h 13 0x0d r/w capacitive offset calibrationhigh byte, 0x80 cap offset l 14 0x0e r/w capacitive offset calibrationlow byte, 0x00 cap gain h 15 0x0f r/w capacitive gain calibrationhigh byte, factory calibrated cap gain l 16 0x10 r/w capacitive gain calibrationlow byte, factory calibrated volt gain h 17 0x11 r/w voltage gain calibratio nhigh byte, factory calibrated volt gain l 18 0x12 r/w voltage gain calibratio nlow byte, factory calibrated 1 the cin2 bit is relevant only for ad7746. the cin2 bit shou ld always be 0 on the ad7745.
ad7745/ad7746 rev. 0| page 15 of 28 status register address pointer 0x00, read only, default value 0x07 this register indicates the status of the converter. the status register can be read via the 2-wire serial interface to query a finished conversion. the rdy pin reflects the status of the rdy bit. therefore, the rdy pin high-to-low transition can be used as an alternative indication of the finished conversion. table 9. status register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic - - - - excerr rdy rdyvt rdycap default 0 0 0 0 0 1 1 1 table 10. bit mnemonic description 7-4 - not used, always read 0. 3 excerr excerr = 1 indicates that the excitati on output cannot be driven properly. the possible reason can be a short circuit or too high capacitance between the excitation pin and ground. 2 rdy rdy = 0 indicates that conversion on the enabled cha nnel(s) has been finished and new unread data is available. if both capacitive and voltage/temperature channels are en abled, the rdy bit is chan ged to 0 after conversion on both channels is finished. the rdy bi t returns to 1 either when data is read or prior to finishing the next conversion. if, for example, only the capacitive channel is enab led, then the rdy bit reflects the rdycap bit. 1 rdyvt rdyvt = 0 indicates that a conversion on the voltage/ temperature channel has been finished and new unread data is available. 0 rdycap rdycap = 0 indicates that a conversion on the capaciti ve channel has been finished and new unread data is available. cap data register 24 bits, address pointer 0x01, 0x02, 0x03, read-only, default value 0x000000 capacitive channel output data. the register is updated after finished conversion on the capacitive channel, with one exception: when the serial interface read operation from the cap data register is in progress, the data register is not updated and the new capacitance conversion result is lost. the stop condition on the serial interface is considered to be the end of the read operation. therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. to prevent losing some of the results, the cap data register should be read before the next conversion on the capacitive channel is finished. the 0x000000 code represents negative full scale (C4.096 pf), the 0x800000 code represents zero scale (0 pf), and the 0xffffff code represents positive full scale (+4.096 pf). vt data register 24 bits, address pointer 0x04, 0x05, 0x06, read-only, default value 0x000000 voltage/temperature channel output data. the register is updated after finished conversion on the voltage channel or temperature channel, with one exception: when the serial interface read operation from the vt data register is in progress, the data register is not updated and the new voltage/temperature conversion result is lost. the stop condition on the serial interface is considered to be the end of the read operation. therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. for voltage input, code 0 represents negative full scale (Cv ref ), the 0x800000 code represents zero scale (0 v), and the 0xffffff code represents positive full scale (+v ref ). to prevent losing some of the results, the vt data register should be read before the next conversion on the voltage/ temperature channel is finished. for the temperature sensor, the temperature can be calculated from code using the following equation: temperature (c) = ( code /2048) ? 4096
ad7745/ad7746 rev. 0 | page 16 of 28 cap set-up register address pointer 0x07, default value 0x00 capacitive channel setup. table 11. cap set-up register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic capen cin2 capdiff - - - - capchop default 0 0 0 0 0 0 0 0 table 12. bit mnemonic description 7 capen capen = 1 enables capacitive channel for single conversion, continuous conversion, or calibration. 6 cin2 cin2 = 1 switches the internal multiplexe r to the second capacitive input on the ad7746. 5 capdiff diff = 1 sets differential mode on the selected capacitive input. 4-1 - these bits must be 0 for proper operation. 0 capchop the capchop bit should be set to 0 for th e specified capacitive channel performance. capchop = 1 approximately doubles the capacitive ch annel conversion times and slightly improves the capacitive channel noise performance for the longest conversion times. vt set-up register address pointer 0x08, default value 0x00 voltage/temperature channel setup. table 13. vt set-up register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic vten vtmd1 vtmd0 extref - - vtshort vtchop default 0 0 0 0 0 0 0 0 table 14. bit mnemonic description 7 vten vten = 1 enables voltage/temperature channel for si ngle conversion, continuous conversion, or calibration. voltage/temperature channe l input configuration. vtmd1 vtmd0 channel input 0 0 internal temperature sensor 0 1 external temperature sensor diode 1 0 v dd monitor 6 5 vtmd1 vtmd0 1 1 external voltage input (vin) 4 extref extref = 1 selects an external reference voltage connect ed to refin(+), refin(C) for the voltage input or the v dd monitor. extref = 0 selects the on-chip internal reference. the internal reference must be used with the internal temperature sensor for proper operation. 3-2 - these bits must be 0 for proper operation. 1 vtshort vtshort = 1 internally shorts the voltage/temperature ch annel input for test purposes. 0 vtchop = 1 vtchop = 1 sets internal chopping on the voltage/temperature channel. the vtchop bit must be set to 1 for the spec ified voltage/temperature channel performance.
ad7745/ad7746 rev. 0| page 17 of 28 exc set-up register address pointer 0x09, default value 0x03 capacitive channel excitation setup. table 15. exc set-up bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic clkctrl excon excb excb exca exca exclvl1 exclvl0 default 0 0 0 0 0 0 0 0 table 16. bit mnemonic description 7 clkctrl the clkctrl bit should be set to 0 for the specified ad7745/ad7746 performance. clkctrl = 1 decreases the excitation signal frequency and the modulator clock freq uency by factor of 2. this also increases the conversion time on all channels (c apacitive, voltage, and temperature) by a factor of 2. 6 excon when excon = 0, the excitation signal is present on the output only during capa citance channel conversion. when excon = 1, the excitation signal is pr esent on the output during both capacitance and voltage/temperature conversion. 5 excb excb = 1 enables excb pin as the excitation output. 4 excb excb = 1 enables excb pin as the inverted excitation output. only one of the excb or the excb bits should be set for proper operation. 3 exca exca = 1 enables exca pin as the excitation output. 2 exca exca = 1 enables exca pin as the inverted excitation output. only one of the exca or the exca bits should be set for proper operation. excitation voltage level. exclvl1 exclvl0 voltage on cap exc pin low level exc pin high level 0 0 v dd /8 v dd 3/8 v dd 5/8 0 1 v dd /4 v dd 1/4 v dd 3/4 1 0 v dd 3/8 v dd 1/8 v dd 7/8 1 0 exclvl1, exclvl0 1 1 v dd /2 0 v dd
ad7745/ad7746 rev. 0 | page 18 of 28 configuration register address pointer 0x0a, default value 0xa0 converter update rate and mode of operation setup. table 17. configuration register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic vtf1 vtf0 capf2 capf1 capf0 md2 md1 md0 default 0 0 0 0 0 0 0 0 table 18. bit mnemonic description voltage/temperature channel digital filter setupconversion time/update rate setup. the conversion times in this table are valid for the clkctrl = 0 in the exc setup register. the conversion times are longer by a factor of two for the clkctrl = 1. vtchop = 1 vtf1 vtf0 conversion time (ms) update rate (hz) C3 db frequency (hz) 0 0 20.1 49.8 26.4 0 1 32.1 31.2 15.9 1 0 62.1 16.1 8.0 7 6 vtf1 vtf0 1 1 122.1 8.2 4.0 capacitive channel digital filter setup conversion time/update rate setup. the conversion times in this table are valid fo r the clkctrl = 0 in the exc setup register. the conversion times are longer by factor of two for the clkctrl = 1. cap chop = 0 capf2 capf1 capf0 conversion time (ms) update rate C3 db frequency (hz) 0 0 0 11.0 90.9 87.2 0 0 1 11.9 83.8 79.0 0 1 0 20.0 50.0 43.6 0 1 1 38.0 26.3 21.8 1 0 0 62.0 16.1 13.1 1 0 1 77.0 13.0 10.5 1 1 0 92.0 10.9 8.9 5 4 3 capf2 capf1 capf0 1 1 1 109.6 9.1 8.0 converter mode of operation setup. md2 md1 md0 mode 0 0 0 idle 0 0 1 continuous conversion 0 1 0 single conversion 0 1 1 power-down 1 0 0 - 1 0 1 capacitance system offset calibration 1 1 0 capacitance or voltage system gain calibration 2 1 0 md2 md1 md0 1 1 1
ad7745/ad7746 rev. 0| page 19 of 28 cap dac a register address pointer 0x0b, default value 0x00 capacitive dac setup. table 19. cap dac a register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic dacaena daca7-bit value default 0 0x00 table 20. bit mnemonic description 7 dacaena dacaena = 1 connects capacitive da ca to the positive capacitance input. 6-1 daca daca value, code 0x00 0 pf, code 0x7f full range. cap dac b register address pointer 0x0c, default value 0x00 capacitive dac setup. table 21. cap dac b register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic dacbenb dacb7-bit value default 0 0x00 table 22. bit mnemonic description 7 dacbenb dacbenb = 1 connects capacitive da cb to the negative capacitance input. 6-1 dacb dacb value, code 0x00 0 pf, code 0x7f full range. cap offset calibration register 16 bits, address pointer 0x0d, 0x0e, default value 0x8000 the capacitive offset calibration register holds the capacitive channel zero-scale calibration coefficient. the coefficient is used to digitally remove the capacitive channel offset. the register value is updated automatically following the execution of a capacitance offset calibration. the capacitive offset calibra- tion resolution (cap offset register lsb) is less than 32 af; the full range is 1 pf. on the ad7746, the register is shared by the two capacitive channels. if the capacitive channels need to be offset-calibrated individually, the host controller software should read the ad7746 capacitive offset calibration register values after performing the offset calibration on individual channels and then reload the values back to the ad7746 before executing conversion on a different channel. cap gain calibration register 16 bits, address pointer 0x0f, 0x10, default value 0xxxxx capacitive gain calibration register. the register holds the capacitive channel full-scale factory calibration coefficient. on the ad7746, the register is shared by the two capacitive channels. volt gain calibration register 16 bits, address pointer 0x11,0x12, default value 0xxxxx voltage gain calibration register. the register holds the voltage channel full-scale factory calibration coefficient.
ad7745/ad7746 rev. 0 | page 20 of 28 circuit description digital filter 24-bit - ? modulator clock generator mux temp sensor cap dac cap dac voltage reference control logic calibration ad7745 vdd ref in(+) refin( ? ) gnd sda scl rdy vin(+) vin(?) cin1(+) cin1( ?) exca excb 05468- 001 i 2 c serial interface excitation f i gur e 2 6 . ad77 45 bl oc k dia g r a m digital filter 24-bit - ? modulator mux temp sensor cap dac cap dac voltage reference control logic calibration ad7746 vdd refin(+) refin(? ) gnd sda scl rdy vin(+) vin(?) cin1(+) cin1( ?) cin2(+) cin2( ?) exc1 exc2 05468- 002 clock generator i 2 c serial interface excitation f i gur e 2 7 . ad77 46 bl oc k dia g r a m overview the ad7745/ad7746 co r e is a hig h p r ecision c o n v er t e r co n- sist in g o f a s e cond o r der (- o r cha r ge b a lancin g) mo d u la tor a nd a t h ir d o r de r dig i t a l f i l t er . i t w o rks as a cd c fo r t h e ca p a - ci t i ve i n p u ts and as a classic a d c fo r t h e vol t a g e i n p u t o r fo r t h e v o l t a g e f r o m a tem p era t ur e s e n s o r . i n addi tion t o t h e con v er t e r , the ad7745 /ad7 746 in teg r a t es a m u l t i p le x e r , a n e x ci ta ti o n so ur ce a n d ca pd a c s f o r th e ca p a - ci t i v e i n p u ts, a tem p er a t ur e s e ns o r , a v o l t a g e r e fer e n c e fo r t h e vol t a g e and t e m p era t ur e in p u ts, a co m p lete clo c k ge n e ra t o r , a co n t r o l a nd c a lib r a t ion lo g i c, a nd a n i 2 c-com p a t i b le s e r i al in t e r f ace . the ad7745 has o n e ca p a c i ti ve in p u t, while t h e ad7746 has tw o c a p a ci t i ve i n p u ts. a l l o t h e r fe a t ur es an d sp e c if ica t ion s a r e iden t i ca l fo r b o t h p a r t s. capacitance-to- d igital converter f i gur e 28 s h o w s th e cd c sim p li f i ed fun c ti o n al d i a g ra m . th e me a s u r e d c a p a c i t a nc e c x i s co nn ect e d bet w een th e e x ci t a ti o n s o ur ce a nd t h e - mo d u la t o r in p u t. a s q ua r e - w a v e exci t a t i on sig n a l is a p plie d o n t h e c x d u r i n g t h e con v ersio n an d t h e m o d u la t o r co n t i n uo us l y sa m p les th e c h a r g e g o in g th r o ugh th e c x . the dig i t a l f i l t er p r o c es s e s t h e m o d u l a t o r ou t p ut, w h ich is a s t r e a m o f 0s and 1s co n t a i nin g th e inf o r m a t io n in 0 an d 1 den s i t y . th e da t a f r o m t h e dig i t a l f i l t er is s c ale d , a p pl yin g t h e ca lib r a t ion co ef f i cien ts, an d t h e f i na l r e su l t can b e r e a d t h r o ug h th e se r i al in t e rfa c e . the ad7745/ad7746 is desig n ed f o r f l o a tin g c a p a ci t i v e s e n s o r s. th er efo r e , b o t h c x p l a t es ha v e t o b e is ola t e d f r o m g r ou nd. digital filter 24-bit - ? modulator clock generator capacitance to digital converter (cdc) 05468-027 excitation da t a exc cin c x f i gure 28. cdc s i mplified b l ock d i agr a m excitation source the tw o exci t a t i o n p i n s e x ca and ex cb a r e i ndep e n d e n t l y p r ogra m m a b l e . t h ey a r e i d en ticall y fun c ti o n al a n d th e r e f o r e ei t h er o f t h em c a n b e us e d fo r t h e ca p a c i t i v e s e n s o r exci t a t i on. on the 2-c h anne l ad7746 usin g a s e p a ra t e exci ta tion p i n f o r e a ch c a p a c i t i ve chan nel is re c o mmende d.
ad7745/ad7746 rev. 0| page 21 of 2 8 capdac the ad7745/ad7746 cd c f u l l -s cale in p u t ra ng e is 4.096 pf . f o r sim p lici ty of ca lc u l a t io n, h o w e ver , t h e fol l o w i n g tex t and dia g ra m s us e 4 pf . th e p a r t c a n accep t a hig h er ca p a ci tan c e o n t h e in p u t and t h e co mm on- m o d e o r o f fs et (n o t -cha n g i n g co m p on en t) c a p a ci tan c e can b e balan c ed b y p r og ra mma b l e on - c h i p c a pd a c s . data cdc exc cin(+) cin( ?) c x c y capdac(+) capdac(?) 05468-010 f i gure 2 9 . usi n g a cap d a c the ca pd a c c a n b e u n dersto o d as a nega t i ve c a p a ci t a n c e co nne c t e d i n t e r n al l y t o t h e ci n p i n. th er e a r e t w o in dep e n d e n t capd a c s, on e co nne c t e d t o t h e cin(+) an d t h e s e con d co nne c t e d t o t h e cin(C). th e re l a t i o n b e tw e e n t h e c a p a c i t a n c e in p u t an d o u t p ut d a t a can b e ex p r ess e d as ( ) ( ) ) ( ) ( ? ? ? + ? t h e c a pd a c s h a ve a 7 - bi t re s o lut i on , mo noto n i c t r ans f e r f u n c t i on, a r e w e l l ma tch e d to e a ch o t h e r , and ha ve a def i n e d t e m p era t ur e co ef f i cien t. th e c a p d a c f u l l ra n g e (a bs ol u t e val u e) is n o t f a c t o r y cali b r a t e d a n d can va r y u p t o 20% wi th t h e man u fac t ur in g p r o c es s. s e e t h e s p e c if ic a t ion s s e c t ion an d typ i cal p e r f o r m a n c e c h a r ac t e r i stics in f i gur e 17. the ca p d a c s a r e s h a r e d b y t h e tw o c a p a ci t i v e cha n n e ls o n t h e ad7746. i f th e capd a c s n e e d t o b e s e t individ u al l y , t h e h o s t c o n t ro l l e r s o f t w a re shou l d rel o a d t h e c a pd a c v a lu e s to t h e ad7746 bef o r e exec u t in g co n v ersio n o n a dif f er en t c h ann e l . single-ended cap a cit i ve in put w h e n c o n f i g u r e d for a s i ng l e - e nd e d mo d e ( t h e c a pdi f f bi t i n th e c a p s e t u p r e g i s t er is s e t t o 0), th e ad7745/ad7746 ci n(C) p i n is di s c o n n e c t e d i n t e r n a l ly . t h e c d c ( w i t h o u t usin g t h e capd a c s) can m e as ur e o n l y p o si ti v e in p u t ca p a ci tan c e in t h e ra n g e o f 0 pf t o 4 pf (s ee f i gur e 30). 0x800000 . . . 0x ffff ff da t a c a pdiff = 0 0 ... 4pf cdc exc cin(+) cin(?) c x 0 ... 4pf capdac(+) off capdac(?) off 05468-024 f i gure 30. cdc s i n g le-ended input m o de the ca p d a c c a n b e us e d fo r pr og ra mma b l e shif t i n g t h e in put ra n g e . th e exam ple i n f i gur e 31 s h o w s h o w to us e t h e f u l l 4 pf cd c s p an t o m e as ur e ca p a ci tan c e betw e e n 0 pf t o 8 pf . 0x000000 . . . 0x ffff ff da t a c a pdiff = 0 4pf cdc exc cin(+) cin(?) c x 0 ... 8pf capdac(+) 4pf capdac(?) 0pf 05468-025 f i gure 3 1 . usi n g ca p d a c i n s i ngle-end ed mo d e f i gur e 32 s h o w s h o w t o s h if t the in p u t ran g e f u r t h e r , u p t o 21 pf a b so l u t e val u e o f ca p a ci tan c e co nn ec t e d to th e cin(+). 0x000000 . . . 0x ffff ff da t a c a pdiff = 0 4pf cdc exc cin(+) cin(?) c x 13 ... 21pf (17 4pf) capdac(+) 17pf capdac(?) 0pf 05468-026 f i gure 3 2 . usi n g ca p d a c i n s i ngle-end ed mo d e differen ti al capaci ti ve in put w h en conf igur e d fo r a dif f er en t i al m o de (t he cap d iff b i t i n th e c a p s e t u p r e g i s t er s e t t o 1), th e ad7745 /ad7746 cd c m e as ur es t h e di f f er en ce b e tw e e n p o si t i ve an d nega t i ve ca p a c i tan c e in p u t. e a ch o f t h e tw o in p u t c a p a ci t a nces c x an d c y b e t w een t h e ex c a n d ci n p i ns m u s t be les s tha n 4 pf (wi t h o u t u s in g the capd a c s) o r m u s t be les s than 21 pf a n d ba l a n c ed b y t h e c a pd a c s . bala n c in g b y th e ca p d a c s m e a n s th a t bo th c x Cca p d a c(+ ) a n d c y Ccapd a c(C) a r e les s tha n 4 pf . i f t h e u n b a lan c e d c a p a ci t a n c e b e tw e e n t h e e x c a n d ci n p i n s is hig h er t h a n 4 p f , t h e cd c i n t r o d uces a ga i n er r o r , a n o f fs et er r o r , a n d n o nli n e a r i ty er r o r . s e e t h e exam p l es s h own in f i gu r e 33, f i gur e 34, a n d f i gur e 35. 0x0000 00 . . . 0xf f f f f f da t a c a pdiff = 1 4pf cdc exc cin(+) cin(?) c x 0 ... 4pf c y 0 ... 4pf capdac(+) off capdac(? ) off 05468-020 f i gure 33. cdc d i ffer e ntial inp u t mod e
ad7745/ad7746 rev. 0 | page 22 of 28 0x 00 000 0 . . . 0 x f f f f f f da t a c a pdiff = 1 4pf cdc exc cin(+) cin(?) c x 15 ... 19pf (17 2pf) c y 15 ... 19pf (17 2pf) capdac(+) 17pf capdac( ?) 17pf 05468-021 f i g u re 34. u s ing ca pda c in d i f f e rent i a l m o d e 0x0000 00 . . . 0xf f f f f f da t a c a pdiff = 1 4pf cdc exc cin(+) cin(?) c x 13 ... 21pf (17 4pf) c y 17pf capdac(+) 17pf capdac(? ) 17pf 05468-011 f i g u re 35. u s ing ca pda c in d i f f e rent i a l m o d e parasit i c c a paci ta nc e to grou n d da t a cdc exc c gnd1 ci n c gnd2 c x 05468-012 f i gure 36. p a r a siti c capa cita nc e to gro u nd the cd c a r c h i t ec t u r e us ed in t h e ad7745 /ad7746 m e as ur es th e ca pa ci ta n c e c x co nn ect e d b e t w een t h e ex c p i n a n d t h e cin p i n. i n t h e o r y , a n y ca p a ci t a n c e c p to g r ou n d s h ou l d not a f f e c t th e cd c r e s u l t (s ee f i gure 36). t h e p r a c ti cal im p l em e n ta ti o n o f th e ci r c ui tr y i n t h e c h i p im plies cer t a i n l i mi t s an d t h e r e su l t is g r ad u a l l y a f fe c t e d b y ca p a c i t a n c e t o g r o u n d . s e e t h e a l lo w e d ca p a ci t a n c e t o gnd in t h e sp e c if ic a t ion t a b l e fo r cin a n d exci t a t i o n . a l s o s e e t h e typ i cal p e r f o r m a n c e c h a r ac t e r i stics sh o w n in f i gur e 9, f i gur e 10, a n d f i gur e 11 . parasitic r e sistance to grou nd da t a cd c exc r gnd1 ci n r gnd2 c x 05468-013 f i gur e 3 7 . p a r a si tic resi sta n c e t o gr o u nd the ad7745/ad7746 cd c r e su l t w o u l d b e a f f e c t ed b y a lea k - a g e c u r r en t f r o m t h e c x t o g r o u nd , t h er efo r e t h e c x sh o u ld be is ola t e d f r o m t h e g r o u n d . the i n f l uen c e o f t h e le aka g e c u r r en t va r i es wi t h t h e p o w e r s u p p l y v o l t a g e . th e fol l o w i n g limi ts c a n b e us e d as a guide l i n e fo r t h e al lo w e d le aka g e c u r r en t o r t h e eq ui v a l e n t r e s i s t a n ce b e t w ee n t h e c x an d g r o u nd (f igur e 37). v dd 5 v : i gnd < 150 na (tha t is, r gnd > 30 m?) v dd 3 v : i gnd < 60 na (tha t is, r gnd > 50 m?) v dd 2.7 v : i gn d < 30 na (tha t is, r gn d > 100 m ? ) a hig h er leaka ge c u r r en t t o g r o u n d r e s u l t s in a ga in er r o r , a n o f fs et er r o r , a n d a n o nli n e a r i ty er r o r . s e e t h e typical p e r f o r ma n c e c h a r ac t e r i s t ics sh o w n in f i gur e 12 a n d f i gur e 13. parasitic parallel re sistance da t a cdc exc ci n r p 05468-022 c x f i gur e 3 8 . p a r a si tic p a r a l l el resi sta n ce the ad7745/ad7746 cd c m e as ur es th e c h a r g e tra n sf er b e tw e e n e x c p i n an d cin pin. an y r e sist an ce c o nn e c te d in p a ral l e l t o th e m e as ur ed ca p a c i tan c e cx (s e e f i gur e 38), s u c h as th e pa ra s i ti c r e s i s t a n ce o f th e sen s o r , also tra n s f e r s c h a r g e . ther efo r e , t h e p a ral l e l r e sis t o r is s e en as a n addi t i o n al ca p a c i t a n c e in t h e o u t p ut da t a . the e q uivalen t p a ral l e l ca p a c i tan c e (o r er r o r ca us ed b y th e p a ral l e l r e sista n ce) can be ap p r ox i m at e l y c a l c u l at e d a s 4 1 = w h er e r p is th e p a ral l e l r e sis t a n ce an d c ex c is t h e exci t a t i on f r e q uen c y . s e e t h e typ i ca l p e r f o r ma n c e cha r ac ter i st ics sh own i n f i gur e 14.
ad7745/ad7746 rev. 0| page 23 of 2 8 p a r a sitic s e rial resist ance da t a cd c exc r s1 ci n r s2 c x 05468-023 f i gur e 3 9 . p a r a si tic seri al res i sta n c e the ad7745/ad7746 cd c r e su l t is a f fec t ed b y a r e sis t a n c e in s e r i es wi t h t h e m e asur e d ca p a c i t a n c e . th e t o t a l s e r i al r e sist an c e , wh ic h r e f e r s t o r s1 + r s2 o n f i gur e 39, s h o u ld b e les s tha n 1 k? fo r t h e sp e c if ie d p e r f o r ma n c e . s e e typ i cal p e r f o r ma n c e cha r ac - t e r i s t ics sh o w n in f i gur e 15. capacitive gain calib r ation the ad7745/ad7746 ga in is fac t o r y cali b r a t e d fo r th e f u l l s c ale o f 4.096 pf in th e p r o d uc tio n fo r eac h p a r t individ u al l y . th e fac t o r y ga in co e f f i cien t is st o r e d in a on e - t i m e pr og ra mma b l e (o t p ) m e m o r y a n d is co p i e d to th e c a p a ci t i v e ga in r e gis t er a t p o w e r - u p o r a f ter r e s e t. the ga i n can b e cha n g e d b y exe c u t in g a ca p a c i t a n c e ga in calib r a t io n m o de , f o r whic h an ext e r n al f u l l -s ca le ca p a c i tan c e n e e d s t o b e co nn ec ted t o th e ca p a ci tan c e in p u t, o r b y wr i t in g a us er val u e t o t h e ca p a c i t i v e gai n r e g i st er . this cha n g e w o u l d b e on l y te m p or ar y an d t h e f a c t or y g a i n c o e f f i c i e n t wou l d b e r e lo aded back af t e r p o w e r - u p o r r e set. t h e p a r t is t e s t e d an d sp e c if ie d o n ly fo r us e wi t h t h e defa u l t f a c t o r y ca li b r a t ion co ef f i cien t. capacitive system offset calib r ation the c a p a ci t i v e o f fs et is do mina t e d b y t h e p a ras i t i c o f fs et in t h e a p plic a t ion, such as t h e ini t ia l c a p a ci t a n c e o f t h e s e n s o r , an y pa ra s i ti c ca pa ci t a n c e o f tra c k s o n th e boa r d , a n d th e ca pa ci t a n c e of an y ot he r c o n n e c t i ons b e t w e e n t h e s e ns or a n d t h e c d c . ther efo r e , th e ad7745/ad7746 a r e n o t fac t o r y calib r a t ed fo r ca p a c i t i v e o f fs et . i t is t h e us er s r e sp o n sib i l i ty t o calib r a t e t h e syst em ca p a c i t a n c e o f fs et i n t h e a p plic a t ion. an y o f fs et in t h e ca p a c i t a n c e in p u t la rg er t h a n 1 pf sh o u ld f i rst b e r e m o v e d usin g t h e o n -chi p cap d a c s. the smal l o f fs et w i t h i n 1 pf ca n th e n be r e m o v e d b y u s i n g th e ca pa ci ta n c e o f fs et cali b r a t ion r e g i st er . on e m e t h o d o f ad j u st ing t h e o f fs et is t o co nne c t a zer o -s cale ca p a c i t a n c e t o t h e i n p u t an d exe c u t e t h e c a p a ci t a nce o f fs et calib r a t ion m o de . the cal i b r a t ion s e ts t h e mid p o i n t o f t h e 4.096 pf ra n g e (tha t is, ou t p u t c o de 0x800000) t o tha t zer o -s c a le in p u t . an o t h e r m e t h o d w o uld be t o calcula t e a n d w r i t e t h e o f fs e t cali - b r a t ion reg i ster val u e , t h e ls b is va l u e 31 .25 af ( 4 .09 6 pf /2 17 ). the o f fs et calib r a t io n r e g i st er i s r e lo ade d b y t h e defa u l t val u e a t p o w e r - o n o r a f ter r e s e t. th er efor e , if t h e o f fs et c a li b r a t ion is n o t r e pea t ed a f t e r ea c h sys t em po w e r - u p , th e cali b r a t i o n coe f f i ci e n t val u e sh o u ld b e st o r e d b y t h e h o st co n t r o l l er a n d r e lo ade d as p a r t o f th e ad7 745/ad7746 s e t u p . on the ad7746 , th e r e g i s t er is sha r ed b y the two ca p a ci t i v e ch an nel s . i f t h e c a p a c i t i ve ch an nel s ne e d to b e of f s e t c a l i b r a t e d i n d i v i d u a l ly , t h e ho st c o n t ro l l e r s o f t w a re shou l d re a d t h e ad7746 c a p a ci t i v e o f fs et calib r a t io n reg i s t er va l u es a f t e r p e r f or m i ng t h e of f s e t c a l i br a t i o n on i n d i v i d u a l c h an nel s a n d th en r e lo ad t h e val u es bac k t o t h e ad7746 befor e exec u t in g a co n v ersio n on a dif f er en t cha n ne l. internal temperatur e sensor digital filter and scaling 24-bit - ? modulator clock generator internal temperature sensor 05468-040 voltage reference da t a in i ? v be v dd f i gure 40. inte rn al t e m p er ature s e ns o r the t e m p er a t ure s e n s in g m e t h o d us ed in t h e ad7745/ad7746 is t o m e asur e a dif f er en ce i n ?v be volt age of a t r ans i stor o p era t e d a t tw o dif f er en t c u r r en ts (s e e f i gur e 40 ). th e ?v be ch ange w i t h te m p e r a t u r e i s l i n e ar an d c a n b e e x pre s s e d a s ) ln( ) ( n q kt n v f be = ? wher e: k is b o l t zm a n n s co n s tan t (1.38 10 C23 ). t is t h e a b s o l u te t e m p era t ur e i n k e lv in. q i s th e c h a r g e o n th e e l ectr o n (1.6 10 C19 co u l o m bs). n i s th e ra ti o o f th e t w o cu rr e n t s . n f is th e ideali ty fac t o r o f th e t h er m a l dio d e . the ad7745/ad7746 us es a n o n -c hi p tra n sis t o r t o m e as ur e t h e t e m p era t ur e o f t h e si licon chi p in side t h e p a ckag e . the - ad c con v er ts t h e ?v be t o dig i t a l , th e da ta a r e s c aled usin g fac t o r y cali b r a t io n co ef f i cien ts, th us th e o u t p u t co de is prop or t i on a l to te m p e r atu r e : () 4096 2048 ? = the ad7745/ad7746 has a lo w p o w e r co n s u m p t ion r e s u l t ing in o n l y a sm al l ef f e c t d u e t o the p a r t se lf-h e a tin g (les s tha n 0.5c a t v dd = 5 v).
ad7745/ad7746 rev. 0 | page 24 of 28 i f th e ca pa ci ti v e se n s o r ca n be c o n s ider e d t o b e a t t h e s a me t e m p era t ur e as t h e ad7745 /ad7746 c h i p , the in t e r n al t e m p era t ur e s e ns o r ca n b e us e d as a syst e m t e m p era t ur e s e n s o r . tha t m e a n s t h e co m p let e syst em t e m p er a t ur e dr if t co m p en s a t i o n c a n be bas e d on th e ad7745 /ad7746 in ter n al te m p e r atu r e s e n s or w i t h out ne e d f o r an y a d d i t i on a l e x te r n a l co m p on e n ts. s e e t h e typ i cal p e r f o r ma n c e cha r ac t e r i st ics in f i gur e 18. external temperatur e sensor digital filter and scaling 24-bit - ? modulator clock generator external temperature sensor 05468-041 voltage reference da t a i . . . n i ? v be v dd vi n ( ?) vi n ( +) r s2 r s1 2n39 06 f i g u re 41. t r ans i s t o r as an e x t e rn al t e mpe r at u r e s e ns or the ad7745/ad7746 p r o v ide th e o p tion o f usin g a n exter n al t r a n sist o r as a t e m p er a t ur e s e n s o r in t h e syst e m . th e ?v be me t h o d , w h i c h i s s i mi l a r to t h e i n te r n a l te m p e r a t u r e s e ns or m e t h o d , i s u s ed . h o w e v e r , i t i s m o d i f i ed t o co m p en sa t e f o r th e se ri al r e s i s t a n ce o f co n n ecti o n s t o th e sen s o r . t o tal se ri al re s i st anc e ( r s1 + r s2 in f i gur e 41 ) u p t o 100 ? is co m p en s a t e d . the vin( C) p i n m u st b e g r o u nde d fo r p r o p er ext e r n al t e m p era t ur e s e ns o r o p era t ion. the ad7745/ad7746 a r e fac t or y cali b r a t ed fo r t r a n sis t o r 2 n 39 06 wi t h t h e idea li ty fac t o r n f = 1.008. s e e t h e typ i cal p e r f o r ma n c e cha r ac t e r i st ics sh o w n in f i gur e 19. voltage in put digital filter 24-bit - ? modulator clock generator analog to digital converter (adc) 05468-042 voltage reference da t a vi n ( ? ) vi n ( + ) re f i n(? ) re f i n( + ) r ref rt d r t vd d gn d f i gure 42. r e sistive t e m p er ature s e ns o r co nnec t ed to th e v o ltag e input the ad7745/ad7746 - co r e ca n w o rk as a hig h r e s o l u tion (u p t o 21 en o b ) classic ad c wi t h a f u l l y dif f er en t i a l v o l t a g e in p u t. th e ad c ca n b e us e d ei t h er wi t h t h e o n - c hi p hig h p r e c isio n, lo w dr if t, 1.17 v v o l t age r e fer e n c e , o r a n ext e r n a l r e fer e n c e co nn e c t e d t o t h e f u l l y dif f er en t i al r e fe r e n c e i n p u t p i ns . the v o l t a g e an d r e fer e n c e in p u t s a r e co n t i n uo usly s a m p le d b y a - mo d u la t o r d u r i n g t h e con v ersio n . th er efo r e , t h e i n p u t s o ur ce im p e dance sh o u ld b e k e p t lo w . s e e t h e a p plica t io n exa m ple in f i gu r e 42. v dd monitor alo n g wi th con v er tin g ext e r n al v o l t a g es, the ad7745/ad7746 - ad c can b e used f o r m o ni t o r i n g th e v dd vo lt a g e . t h e v o l t a g e f r o m t h e vd d p i n is in t e r n al l y a t t e n u a t ed b y 6. ty pical a p plicati o n diagram digital filter 24-bit - ? modulator clock generator mux temp sensor cap dac cap dac excitation voltage reference control logic calibration ad7745 vdd refin(+) refin(?) gnd sda scl rdy vin(+) vin(? ) cin1(+) cin1(? ) exca excb 05468-008 host system + 0.1 f 10 f 3v/5v power suppl y i 2 c serial interface 10k ? 10k ? f i gure 43. bas i c a p plic ation d i agr a m fo r a di ffer e nt i a l ca paci ti v e senso r
ad7745/ad7746 rev. 0 | page 25 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab f i gure 44. 1 6 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 16) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad7745aruz 1 C40c to +125c 16-lead tssop ru-16 ad7745aruz-reel 1 C40c to +125c 16-lead tssop ru-16 ad7745aruz-r eel7 1 C40c to +125c 16-lead tssop ru-16 ad7746aruz 1 C40c to +125c 16-lead tssop ru-16 ad7746aruz-reel 1 C40c to +125c 16-lead tssop ru-16 ad7746aruz-r eel7 1 C40c to +125c 16-lead tssop ru-16 eval-ad7746 e b e v a l u a t i o n boar d 1 z = pb-free part.
ad7745/ad7746 rev. 0 | page 26 of 28 notes
ad7745/ad7746 rev. 0 | page 27 of 28 notes
ad7745/ad7746 rev. 0 | page 28 of 28 notes pur c has e of licens ed i 2 c c o m p o n en ts o f analog d e vic e s o r o n e o f i t s s u b l ic en s e d a s s o c i a t e d c o m p a n ies c o n v e y s a lic e n s e f o r t h e p u r c ha s e r un d e r t h e p h i li ps i 2 c p a t e n t r i gh ts t o use t h es e c o m p o n en t s in a n i 2 c sys t em, p r o v id e d t h a t t h e sys t em c o nf o r m s t o t h e i 2 c s t a n da r d s p e c ifica t io n a s defin e d b y p h i l i p s. ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c05468-0-4/05(0)

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